This invention relates in general to clock generators and relates more particularly to clock generators that provide a pair of nonoverlapping clock signals.
As clock periods become shorter, the effects of signal delays within a circuit become increasingly important. For signal processing in closely spaced circuits on an integrated circuit (IC), the delay of a clock signal in reaching on-chip components is critical, because, the states of on-chip components change in response to the transitions of the clock at the locations of those components. This is dependent on the delays of the clock signals travelling from the clock generator to these circuits.
As ICs become larger, there is an increased amount of clock signal delay. Therefore, it becomes useful to have a second staggered clock signal to help control signal processing. It is increasingly common to include on a chip a clock generator that, from an input clock signal produces two or more staggered clock signals for use on that chip. This enables various actions to be staggered at intervals smaller than the rate of the input clock signal. If these two clock signals experience the same delay in reaching all circuits, then the delay problem will be solved. Unfortunately, these two clock signals will not experience identical delays to all components on an IC.
The relative delay (i.e., the skew) between these clock signals has a significant effect on processing in ICs. At the present time, skew of up to 5 nanoseconds is not uncommon. Such skew is important if it is comparable to the period of a clock signal. If this occurs, then the two clock signals will not be synchronous. For a 20 MHz clock, such as is readily available today, each clock period is 50 nanoseconds. Therefore, a pair of 20 MHz clock signals can be offset by no more than 25 nanoseconds. It is the ratio of skew to clock period that is important in determining whether IC designs will be affected by clock skew. This problem will become greater as clock rates increase further. In particular, for a pair of 100 MHz clock signals, a 5 nanosecond skew will convert nonoverlapping clock signals into overlapping clock signals.
When circuits are enabled by the binary one state of two staggered clock signals, it is important that only one of these two clock signals be in the binary one state at any given circuit at a given time. These two clock signals are said to be "nonoverlapping" if only one of these clock signals is in a binary one state at a given time over the entire IC. This definition and the discussion below is given in terms of positive logic circuitry, but the case of negative logic circuitry is equivalent.
FIG. 1 illustrates a clock generator that, in response to an input clock signal C produces a pair of output clock signals .phi..sub.1 and .phi..sub.2. A positive edge D-type flip-flop 11 and a negative edge D-type flip-flop 12 each has its clock input responsive to the input clock signal C and has its reset input responsive to an input reset signal R. An intermediate signal Q.sub.1 is produced at the Q output of flip-flop 11 and an intermediate signal Q.sub.2 is produced at the Q output of flip-flop 12. Q.sub.1 is supplied to the D input of flip-flop 11, to an input of an AND gate 13 and to an inverting input of an AND gate 14. Q.sub.2 is supplied to the D input of flip-flop 12, to an input of an AND gate 13 and to an inverting input of an AND gate 14. Output clock signals .phi..sub.1 and .phi..sub.2 are produced at the outputs of AND gates 13 and 14, respectively.
The operation of this circuit can be understood by consideration of the signal timing diagram in FIG. 2. .phi..sub.1 is high only if both Q.sub.1 and Q.sub.2 are high, whereas .phi..sub.2 is high only if both Q.sub.1 and Q.sub.2 are low. These two conditions are mutually exclusive, so this circuit produces nonoverlapping clock signals .phi..sub.1 and .phi..sub.2. In the ideal case in which input clock signal C has a 50% duty cycle and signal delays through the two flip-flops are equal, output clock signals have 25% duty cycles, have a frequency that is half of input clock signal C and are offset by one-half cycle.
Unfortunately, there is a large delay for the clock input signal to pass through the flip-flops. Any difference in delay between these two flip-flops will affect the duty cycle of the output clock signals. Contemporary logic gates can exhibit propagation delays that range from values on the order of or less than one nanosecond to values on the order of or greater than ten nanoseconds, depending on the IC digital logic family used to implement the gates. Because the delay through a D-type flip-flop can be 5 times larger than logic gates, the duty cycle of output clock signals .phi..sub.1 and .phi..sub.2 can be significantly affected by variations in relative delay time for flip-flops 11 and 12. The average delay through flip-flops 11 and 12 will delay the action of other circuits responsive to clock signals .phi..sub.1 and .phi..sub.2. If each of two or more chips contains a clock generator like that in FIG. 1 to generate a pair of on-chip clock signals .phi..sub.1 and .phi..sub.2 from the same input clock signal C, the output signals from these different chips can be nonsynchronous. Therefore, it is advantageous to minimize the delay introduced by the on-chip clock generator.
Another disadvantage of the clock generator of FIG. 1 is that the clock rate of output clock signals .phi..sub.1 and .phi..sub.2 is half that of input clock signal C. FIG. 5 illustrates a clock generator that overcomes this limitation. At time t=t.sub.0, a leading edge of a positive pulse of an input clock signal C is applied to an input port 51 of the clock generator. This input clock signal is applied through a delay element 53 to a first input A of an AND gate 52 and is also applied directly to a second input B of AND gate 53. This produces, at an output port 54 connected to the output of AND gate 53, a first output clock signal .phi..sub.1 having a leading edge that is delayed relative to clock signal C by a time D.sub.3 equal to the delay of delay element 52. Similarly, input clock signal C is also applied through an invertor 55 and a delay element 56 to a first input D of an AND gate 57 as well as through invertor 55 directly to a second input E of AND gate 57. This produces on an output port 57 connected to the output of AND gate 58 an output clock signal .phi..sub.2. In this embodiment, delay elements 52 and 56 each consists of a set of four inverters 59 connected in series.
The operation of this circuit is illustrated in the timing diagram of FIG. 6. The input clock has a period P and positive pulses of width W. In the interval from t=t.sub.0 to t=t.sub.1 .ident.t.sub.0 +D.sub.3, signal A is low and signal B is high so that .phi..sub.1 is low. From time t=t.sub.1 to t=t.sub.2 .ident.t.sub.0 +W (where W is the width of a clock pulse), signals A and B are both high so that .phi..sub.1 is high. From time t=t.sub.2 to t=t.sub.3 .ident.t.sub.1 +W, signal A is high and signal B is low so .phi..sub.1 is low. From time t=t.sub.3 to t=t.sub.4 .ident.t.sub.0 +P, signals A and B are both low so that .phi..sub.1 remains low. Therefore, output clock signal .phi..sub.1 has the same period P as input clock signal C. The width W.sub.0 of the positive pulses of output clock signal .phi..sub.1 is W-D.sub.3.
The generation of output clock signal .phi..sub.2 is similar to that of .phi..sub.1, except that there is an extra inversion and delay introduced by invertor 55. If clock C had a 50% duty cycle, if the delay D.sub.3 of delay element 52 were equal to the delay D.sub.4 of delay element 56 and if the delay of invertor 55 were negligible, then this circuit would ensure that output clock signals .phi..sub.1 and .phi..sub.2 were 180.degree. out of phase. More importantly, if the delay of invertor 55 were negligible, then high state pulses of .phi..sub.1 could occur only if clock signal C were high and high state pulses of .phi..sub.2 could occur only if clock signal C were low, thereby ensuring that these two output clock signals are nonoverlapping. For an invertor 55 delay less than D.sub.3, these two clock signals will be nonoverlapping.
Unfortunately, because the width W.sub.0 of the output pulses of the output clock signal are W-D.sub.3, if the delay D.sub.3 becomes comparable to W, then the width of these pulses can become unusably narrow and can even vanish. The delays D.sub.3 and D.sub.4 are functions of temperature, applied voltages, and manufacturing process and can produce variations in delays that vary by a factor of 4 from minimum to maximum values. These variations in delays are large enough to enable D.sub.3 to vary over a range that makes the output pulse width vanish. As D.sub.3 varies through this value, not only could the pulse width temporarily vanish, in addition, D.sub.3 could begin to exceed W. If it does, then the output pulse transitions would jump from the trailing edges of pulses of B to the leading edge of these pulses. If the duty cycle of the input clock signal were 50%, this jump would produce a sudden phase shift of the output clock signal by 180.degree.. IC functionality will be disrupted if the pulse width of the output clock signal vanishes or the phase of the output clock signal jumps suddenly.
FIG. 7 shows another prior art clock generator that is designed to produce a pair of nonoverlapping clock signals of frequency f from an input clock signal of frequency f. An input clock is applied to an input port 71 that is connected directly to a first input of a first NOR gate 72 and is connected through an invertor 73 to a first input of a second NOR gate 74. The output of NOR gate 72 is connected to an output port 75 and the output of NOR gate 74 is connected to an output port 76. The output clock signal .phi..sub.1 produced on output port 75 is fed back to a second input of NOR gate 72 and the output clock signal .phi..sub.2 produced on output port 76 is fed back to a second input of NOR gate 74.
The operation of this circuit can be understood by reference to the timing diagram in FIG. 8. In interval a, because input clock signal C is high, NOR gate 72 drives .phi..sub.1 low as indicated by arrow 81. In interval b, because signal A is high, NOR gate 74 drives .phi..sub.2 low as indicated by arrow 82. In interval c, because signals C and .phi..sub.2 are both low, NOR gate 72 drives .phi..sub.1 high as indicated by arrows 83 and 84. In interval d, because signals A and .phi..sub.1 are both low, NOR gate 74 drives .phi..sub.2 high, as indicated by arrows 85 and 86. However, in interval e, because signals C and A are both low, .phi..sub.1 and .phi..sub.2 are constrained only that one is high and the other is low. In this interval, the signal is unstable and can be a linear sum of components for which .phi..sub.1 =-.phi..sub.2 and oscillates between 0 and 1 at a multiple of the period at which a signal can travel around the loop from the output of NOR gate 72 to the second input of NOR gate 74 and then back from the output of NOR gate 74 to the second input of NOR gate 72. More important than possible unstable portions of output clock signals, are output signals having a nearly 50% duty cycles because then only a small amount of clock skew will result in these signals overlapping.